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High-Level Synthesis of Digital Circuits
Jendrušák, Ján ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
This thesis deals with practical test of high-level synthesis as a digital circuits design method and its current progress in creating RTL models. At first main tasks of HLS will be described together with C++ library of classes called SystemC, which implements hardware constructs, notion of time and hardware datatypes with arbitrary bit width. After that thesis focuses on discrete Fourier transform and its fast form of computation – fast Fourier transform. In the practical part of thesis reference FFT model is written in C++ language, which is later edited appropriately a synthesized with Stratus High-Level Synthesis tool into several hardware architectures.
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HLS development tool for DSP with custom programming language
Pastušek, Václav ; Dvořák, Vojtěch (referee) ; Fujcik, Lukáš (advisor)
Nowadays, there are many different high-level syntheses for describing digital circuits. The best known ones generate VHDL code from programming languages such as ANSI C, C++, SystemC, SystemVerilog and MATLAB. But not everyone will identify with that type of programming, so sometimes it's good to go to a higher level of abstraction, where the internals of the components are hidden, and then the components are called with inputs and outputs. This thesis deals with the design of HLS, the design of input pseudocode, pseudo-libraries, compiler created in Python, its modules and practical application.
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HDR Tone-Mapping Acceleration on Xilinx Zynq Platform
Nosko, Svetozár ; Zemčík, Pavel (referee) ; Musil, Martin (advisor)
This diploma thesis focuses on the High-level synthesis (HLS). The first part deals with theoretical details and methods that are used in HLS tools. This is followed by a description of the synthesis tool Vivado HLS which will be used for implementation of an application. In the second part is briefly introduced high dynamic range images (HDR) and tone mapping. The third part is dedicated to design and implementation of the aplication which implements tone mapping methods in HDR images. This methods are implemented in Vivado HLS and language C++. This application is based on platform Xilinx Zynq and it uses multiexposure camera for capturing HDR images. Images are transmitted to FPGA for tone mapping processing.
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Acceleration of NAT and Packet Filter in FPGA for 10G Networks
Orsák, Michal ; Kořenek, Jan (referee) ; Viktorin, Jan (advisor)
This thesis deals with the design of a universal hardware acceleration unit for packet filtering in FPGA for 10G networks. Maximum count of rules is greatly increased by the use of external QDR-II memory. Parameters of accelerator are suitable for NAT, packet filtering and lawful interceptions. The platform uses variable number of processing units. One of them controls accelerator by USB port. The rest is used for network processing.
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Multimedia Player for iOS
Singh, Kevin ; Číka, Petr (referee) ; Grabovský, Štěpán (advisor)
Diploma work „Multimedia player for iOS“ deals with the description of the video formats such as HLS, MP4, MPEG Transport Stream, and Dash. Next, it continues with protected content DRM, VAST advertisements and analytics tool called Google Analytics. During compilation of this diploma work was created a framework in programming language Swift. This framework is basically a player, that besides playing Interactive videos is able to show ads, subtitles, can change the video quality, AirPlay and download the content for offline playing. A feature to play a protected content could not be done as a developer's request for a product deployment SDK Fairplay was refused from an SDK owner. A testing app was also created that implements developed a framework and prove the functionality of the developed functions.
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Multimedia Player for Android
Benedikt, Jan ; Číka, Petr (referee) ; Grabovský, Štěpán (advisor)
This thesis aims to create an advanced multimedia player with support of an adaptive stream, securing of the multimedia content and support for playing advertisement. The first part explains the used technologies followed by an analysis of available solutions and the comparison between the two. The theoretical framework is then used to create a player library and a testing application. The player library is based on the framework of ExoPlayer application. Whole application is created in Java for the operation system Android OS.
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Stress Testing of Video Streaming Services
Kříž, Petr ; Ilgner, Petr (referee) ; Číka, Petr (advisor)
The bachelor thesis deals with the load testing of services for adaptive streaming of multimedia content. The thesis starts with a theoretical discussion of load testing and standards for adaptive streaming. The practical part deals with the creation of scenarios for load testing the created streaming server. Finally, graphs are prepared including commenting on the testing result.
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Tool for Immediate Subtitles in Running Lecture
Pokorný, Filip ; Bartík, Vladimír (referee) ; Kolář, Dušan (advisor)
This thesis deals with solving problems of Alfons consulting center, specifically of their simultaneous transcript service for the hearing-impaired students. Thanks to my regular attendance in the consulting center, I analyzed the problem and designed an app solution that I then programmed. The goal of this app is to receive a text from people realizing the simultaneous transcript and give it to students in the most suitable form which they can use along with the speaker's video projection. The conclusion of the thesis shows the evaluation of my analysis after trying the app in lessons with deaf students.
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Implementation of Statistical Functions Using HLS
Šinaľ, Peter ; Martínek, Tomáš (referee) ; Dvořák, Milan (advisor)
The aim of this thesis was to design and implement selected statistical functions used in technical analysis. I focused on moving averages, Black-Schles model for calculating option prices and Indicator Delta. These functions are through HLS transformed into an appropriate description for programmable FPGA. During the transformation process, emphasis is on low latency and resource consumption. Created solutions demonstrate the potential of HLS. They show complexity of the technical analysis and hardware requirements. Achieved results show high accuracy in the simulations. Deviation from the reference value is approximately 6,615*10e-3. The results also indicate thet that reducing latency does not necessarily cause an increase in the consumption of resources on the chip.
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